As critical dimensions (CD) of ICs shrink, the metal fill in a RMG process becomes difficult. The RMG process requires forming a gate opening in a dielectric layer and filling the gate opening with gate materials. As gate dimensions shrink, the gate opening may be inadequate to fill such that the metal pinches off, thereby resulting in high gate resistance.
Advanced nodes are now employing one or more recesses of either gate work function material (WFM), gate metal fill, or gate spacer and dielectric gap fill over the gates to enable placing the source/drain (S/D) contacts in close proximity for technology scaling. However, the above schemes add new process challenges to control final gate heights across different gate widths (viz. short vs. long) and multi-threshold voltage (Vt) architectures. Some common issues include high-K damage and WFM loss over the gate fin and final gate height inconsistencies, leading to varying self-aligned contact (SAC) cap budgets, which can cause S/D to gate electrode shorts resulting in device performance degradation.
A need therefore exists for methodology enabling improved metal fill and gate height control across short and long channel lengths or gate widths, and the resulting device.
An aspect of the present disclosure is a method of controlling NFET and PFET gate heights including chamfering p-type work function (pWF) and n-type work function (nWF) metals.
Another aspect of the present disclosure is a device including NFET and PFET regions with chamfered pWF and nWF metals.
Another aspect of the present disclosure is a method of controlling short channel and long channel gate heights including chamfering pWF and nWF metals.
Another aspect of the present disclosure is a device including short channel and long channel regions with chamfered pWF and nWF metals.
Additional aspects and other features of the present disclosure will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present disclosure. The advantages of the present disclosure may be realized and obtained as particularly pointed out in the appended claims.
According to the present disclosure, some technical effects may be achieved in part by a method including: forming an interlayer dielectric (ILD) over a silicon (Si) fin; forming first and second cavities in the ILD, each over and perpendicular to the Si fin; forming a high-K dielectric layer over the ILD and in each of the first and second cavities; forming a pWF metal layer over the high-K dielectric layer in the first cavity; recessing the pWF metal layer to a first height above the fin; forming an nWF metal layer in the first and second cavities over the high-K dielectric layer and the pWF metal layer; recessing the nWF metal layer to a second height, above an edge of the pWF metal layer; forming a barrier metal layer over the high-K dielectric layer and nWF metal layer; filling the first and second cavities with low-resistive metal fill; removing portions of the low-resistive metal fill by chemical mechanical planarization (CMP); and recessing the barrier metal layer and the high-K dielectric layer, to a third height, above an edge of the nWF metal layer, and concurrently etching the low resistive metal fill.
Another aspect of the present disclosure includes recessing each of the pWF and nWF metal layers by chamfering. Further aspects include chamfering by spin-on hard-mask or optical planarization layer (SOH/OPL) coating, reactive ion etching (RIE) and WFM wet etch removal. Other aspects include forming the high-K dielectric layer to a thickness of 5 angstrom (Å) to 25 Å. Additional aspects include forming the pWF metal layer of titanium nitride (TiN) to a thickness of 5 Å to 50 Å. Further aspects include forming the barrier metal layer to a thickness of 25 Å to 75 Å. Another aspect includes recessing the pWF metal layer to the first height of 2 nm to 25 nm above the Si fin. Other aspects include recessing the nWF metal layer to the second height of 4 nm to 30 nm above the Si fin. Additional aspects include recessing the barrier metal layer and the high-K dielectric layer to the third height of 9 nm to 35 nm above the Si fin. Further aspects include recessing the barrier metal layer and the high-K dielectric layer and etching the low-resistive metal by RIE, the low-resistive metal forming a bump extending to a height of 14 nm to 40 nm above the Si fin. In addition, the WFM heights above can be further optimized for gates with different fin heights and gate critical dimensions (CDs).
A further aspect of the present disclosure is a device including: an ILD over a Si fin; first and second cavities in the ILD, each over and perpendicular to the Si fin; a high-K dielectric layer on side and bottom surfaces of the first and second cavities; a pWF metal layer over the high-K dielectric layer in the first and second cavities; an nWF metal layer over the pWF metal layer and over edges of the pWF metal layer in the first cavity and over the high-K dielectric layer in the second cavity; a barrier metal layer over the nWF metal layer and over edges of the nWF layer; and low resistive metal filling the first and second cavities and forming a bump at a center of each cavity.
Aspects of the device include the high-K dielectric layer having a thickness of 5 Å to 25 Å. A further aspect includes the low-resistive metal bump extending to a height of 14 nm to 40 nm above the Si fin. Another aspect includes the pWF metal layer having a thickness of 5 Å to 50 Å. A further aspect includes the barrier metal layer having a thickness of 25 Å to 75 Å.
Another aspect of the present disclosure is a method including: forming an ILD over a Si fin; forming first and second cavities in the ILD over and perpendicular to the Si fin, the first cavity having a greater width than the second cavity; forming a high-K dielectric layer to a thickness of 5 Å to 25 Å over the ILD and in the first and second cavities; forming a pWF metal layer by atomic layer deposition (ALD) to a thickness of 5 Å to 50 Å in the first and second cavities; recessing the pWF metal layer by chamfering to a first height of 2 nm to 25 nm above the Si fin; forming an nWF metal layer by ALD in the cavities over the exposed high-K dielectric layer and the pWF metal layer; recessing the nWF metal layer by chamfering to a second height of 4 nm to 30 nm above the Si fin, but covering an edge of the pWF metal layer; forming a barrier metal layer by either metal organic chemical vapor deposition (MOCVD), ALD, physical vapor deposition (PVD) to a thickness of 25 Å to 75 Å over the high-K dielectric layer and the nWF metal layer; filling the first and second cavities with low-resistive metal; removing portions of the low-resistive metal fill by CMP; and performing RIE, recessing the barrier metal layer, the high-K dielectric layer, and the low-resistive metal to a third height of 9 nm to 35 nm above the Si fin except for a low-resistive metal bump or a final gate height extending to 14 nm to 40 nm above the Si fin at a center of each cavity.
Aspects of the method include chamfering the pWF and nWF metal layers by a maskless process including SOH/OPL coatings, RIE and WFM wet etch removal. Another aspect include the first cavity forming a long channel device, and the second cavity forming a short channel device, the method further including controlling a height of the final gate height in the first and second cavities in the first and second cavities. Other aspects include forming a width of the long channel device to 2 to 12 times the width of the short channel device. Additional aspect includes chamfering the long channel device and the short channel device simultaneously.
Additional aspects and technical effects of the present disclosure will become readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present disclosure are described simply by way of illustration of the best mode contemplated to carry out the present disclosure. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.